The present disclosure relates to a semiconductor memory device and, more particularly, to a precharge voltage supplying circuit.
Recently, the capacity of semiconductor memory devices is rapidly becoming larger and studies on methods to increase an operational speed and reduce current consumption are steadily conducted. Particularly, techniques to reduce the current consumption are developed in a semiconductor memory device which can be embedded in a portable system such as a cellular phone or a notebook computer.
One of the above mentioned techniques is to minimize the current consumption in a core area of a memory. The core area having a plurality of memory cells, bit lines and word lines is designed according to a critical design rule. Thus, the memory cells can be very small and operate with a low power consumption.
Particularly, a bit line precharge technique is important to increase the speed of a cell data access. The bit line precharge technique precharges a bit line (BL) to a half level of a core voltage (VCORE) before the data access in order to increase the speed of the data access.
Meanwhile, in a standby state, a potential difference occurs between a word line (WL) of 0V and a precharged bit line (BL). If a bridge occurs between the word line (WL) and the bit line (BL), a current consumption increases due to the bridge current which is caused by the potential difference. Therefore, in order to reduce the current consumption caused by the bridge current, a precharge voltage supplying circuit, which has a bleeder resistance, is used to generate a precharge voltage (VBLP) on the bit line where a voltage drop occurs.
FIG. 1 is a block diagram of a conventional precharge voltage supplying circuit.
As shown in FIG. 1, the conventional precharge voltage supplying circuit includes a precharge voltage supplying unit 100 for outputting a precharge voltage VBLP by using an internal voltage Vp in response to a clock enable signal CKE.
The precharge voltage supplying circuit outputs the precharge voltage VBLP in response to the clock enable signal CKE of a high level in a normal active state and of a low level in a power down mode.
However, in such a precharge voltage supplying circuit, the clock enable signal CKE can be either in a high level or in a low level at the time of a power-up. Thus, there is a problem that a DRAM wrongly operates since the precharge voltage VBLP is not normally supplied to the bit line and a corresponding bit bar line.